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    Try to Reach 100M Bandwidth Goal with ORS

    Try to Reach 100M Bandwidth Goal with ORS
    • Last Update:2024-05-15
    • Version:001
    • Language:en

    Hardware description

    The GC0802 chip has been soldered in place of an AD9361 on the SDR board of the ORS. This SDR board if open hardware and you can find the schematics/gerbers on our public git repository : https://lab.nexedi.com/nexedi/ors-hardware/-/tree/master/hardOrsTypeA.

    The main points to remember about this board:

    • it already works fine with AD9361
    • the FPGA is a XC7A35T and we can easily recompile the firmware
    • for now the AD9361 is only supported in FDD mode even for TDD signals
    • the FPGA is connected to the PC through a PCIe driver

    Our Goals

    Goal 1

    Make the GC0802 work in FDD mode in 10/20/40 MHz bandwidth (exactly the same as we do with AD9361 now). This goal shouldn't need to change the current FPGA firmware. After goal 1 is reached, we should evaluate the quality of radio signal sent by GC0802.

    Goal 2

    Make the GC0802 work in TDD mode. For this, we will need to change the FPGA firmware to send correctly the samples.

    Goal 3 (ultimate goal)

    Make the GC0802 work in TDD mode in 2x2 MIMO in 100MHz bandwidth.

    Current status

    For now, note that we are only working in FDD 20MHz bandwidth.

    Initialization

    We can initialize the GC0802 only for certain frequencies:

    Now, I tried to use different tx_flo values between 3600MHz and 3800MHz, many values of tx_flo fail. Only very few of them succeed (I tested each 1 MHz):  

    • 3649 MHz
    • 3732 MHz
    • 3733 MHz
    • 3734 MHz
    • 3735 MHz
    • 3736 MHz
    • 3737 MHz
    • 3738 MHz
    • 3739 MHz
    • 3740 MHz
    • 3741 MHz
    • 3742 MHz
    • 3743 MHz
    • 3745 MHz

    I'm using a xtal oscillator at 38.4MHz

    here is a log of succeeding initialisation:

    in detect_chip
detect_chip in line 1535 Success to detect transceiver device in spi bus
phy version: V2.8.25-2023_12_06
Val = 0x22.
chipInfo->low_freq = 200 MHz.
chipInfo->high_freq = 5000 MHz.
chipInfo->low_bandwidth = 12 KHz.
chipInfo->high_bandwidth = 100000 KHz.
chipInfo->tx_num = 2.
chipInfo->rx_num = 2.
chipInfo->chip_ver = 1.
rcal in line 1176 phy->r_cal result is 0x27
auxadc_cal in line 1240, auxadccal_slope is -9, and auxadccal_ordinate is -31
Val = 0x22.
chipInfo->low_freq = 200 MHz.
chipInfo->high_freq = 5000 MHz.
chipInfo->low_bandwidth = 12 KHz.
chipInfo->high_bandwidth = 100000 KHz.
chipInfo->tx_num = 2.
chipInfo->rx_num = 2.
chipInfo->chip_ver = 1.
[0x23 0x09 0x15] [0x02 0x09]
Enable Filter used Fir.
voltage[3]=515
voltage[3]=516
syspll lock failed ! flo=3741000000 voltage=91
voltage[3]=518
voltage[3]=517
syspll lock failed ! flo=3740000000 voltage=91
voltage[3]=517
voltage[3]=517
syspll lock failed ! flo=3740040000 voltage=91
voltage[3]=512
voltage[3]=512
syspll lock failed ! flo=3740040000 voltage=91
 band_dep_calibr_phase_of_switch_bandwidth in line 173, Cur Bandwidth is 3
Rx dc offst cal version=2 
voltage[3]=516
voltage[3]=517
[fn_tx_qec_lol_cal_rflp,152] sample_rate=15360000
voltage[3]=518
voltage[3]=518
voltage[3]=514
voltage[3]=513
voltage[3]=512
voltage[3]=512
voltage[3]=514
voltage[3]=512
voltage[3]=514
voltage[3]=515
voltage[3]=516
voltage[3]=516
voltage[3]=518
voltage[3]=518
voltage[3]=533
voltage[3]=532
voltage[3]=556
voltage[3]=557
voltage[3]=515
voltage[3]=515
voltage[3]=503
voltage[3]=503
voltage[3]=720
voltage[3]=720
voltage[3]=517
voltage[3]=517
voltage[3]=870
voltage[3]=869
Dir=1 lock failed ! flo=3744360000 voltage=869
voltage[3]=942
voltage[3]=941
Dir=1 lock failed ! flo=3744840000 voltage=941
voltage[3]=1003
voltage[3]=1003
Dir=1 lock failed ! flo=3745320000 voltage=1003
voltage[3]=514
voltage[3]=514
voltage[3]=518
voltage[3]=518
voltage[3]=532
voltage[3]=532
voltage[3]=556
voltage[3]=553
voltage[3]=515
voltage[3]=515
voltage[3]=652
voltage[3]=651
voltage[3]=516
voltage[3]=516
voltage[3]=794
voltage[3]=794
voltage[3]=868
voltage[3]=866
Dir=1 lock failed ! flo=3744360000 voltage=866
voltage[3]=941
voltage[3]=940
Dir=1 lock failed ! flo=3744840000 voltage=940
voltage[3]=513
voltage[3]=513
voltage[3]=1028
voltage[3]=1026
Dir=1 lock failed ! flo=3745800000 voltage=1026
[fn_rx_qec_cal,531] sample_rate=15360000
voltage[3]=516
voltage[3]=515
voltage[3]=518
voltage[3]=518
rx_dc_tracking_action_start in line 593 TRX_CHN1 task has been started.
rx_dc_tracking_action_start in line 593 TRX_CHN1 task has been started.
rx_dc_tracking_action_start in line 593 TRX_CHN1 task has been started.
rx_dc_tracking_action_start in line 593 TRX_CHN1 task has been started.
rx_dc_tracking_action_start in line 593 TRX_CHN1 task has been started.

    here is a log of failing initialisation:

    in detect_chip
detect_chip in line 1535 Success to detect transceiver device in spi bus
phy version: V2.8.25-2023_12_06
Val = 0x22.
chipInfo->low_freq = 200 MHz.
chipInfo->high_freq = 5000 MHz.
chipInfo->low_bandwidth = 12 KHz.
chipInfo->high_bandwidth = 100000 KHz.
chipInfo->tx_num = 2.
chipInfo->rx_num = 2.
chipInfo->chip_ver = 1.
rcal in line 1176 phy->r_cal result is 0x27
auxadc_cal in line 1240, auxadccal_slope is -9, and auxadccal_ordinate is -31
Val = 0x22.
chipInfo->low_freq = 200 MHz.
chipInfo->high_freq = 5000 MHz.
chipInfo->low_bandwidth = 12 KHz.
chipInfo->high_bandwidth = 100000 KHz.
chipInfo->tx_num = 2.
chipInfo->rx_num = 2.
chipInfo->chip_ver = 1.
[0x23 0x09 0x15] [0x02 0x09]
Enable Filter used Fir.
voltage[3]=851
voltage[3]=902
Dir=0 lock failed ! flo=3751000000 voltage=902
syspll lock failed ! flo=3751000000 voltage=91
voltage[3]=518
voltage[3]=519
syspll lock failed ! flo=3750000000 voltage=91
voltage[3]=509
voltage[3]=509
syspll lock failed ! flo=3750040000 voltage=91
voltage[3]=509
voltage[3]=509
syspll lock failed ! flo=3750040000 voltage=91
 band_dep_calibr_phase_of_switch_bandwidth in line 173, Cur Bandwidth is 3
Rx dc offst cal version=2 
voltage[3]=818
voltage[3]=920
Dir=0 lock failed ! flo=3751000000 voltage=920
[fn_tx_qec_lol_cal_rflp,152] sample_rate=15360000
voltage[3]=854
voltage[3]=819
voltage[3]=917
voltage[3]=975
Dir=0 lock failed ! flo=3749040000 voltage=975
voltage[3]=923
voltage[3]=948
Dir=0 lock failed ! flo=3749040000 voltage=948
voltage[3]=510
voltage[3]=511
Failed to fn_tx_qec_lol_cal_rflp in chn :0
tx qec lol cal fail!
run band_dep_calibr_phase_of_switch_bandwidth fail!

    Note that the function main_init can finish for all frequencies if we put the flag "tx_qec_flag" to 0.

     

    Outputting a simple signal (1 tone)

    We can output a signal with only one frequency in it after initializing the chip (for example, at 3740MHz). But we see the frequency of this tone inverted compared to what we expected. For example, we expected to see the tone at 3745MHz, but we see it at 3735MHz: we see -5MHz instead of +5MHz.

    Note1: if we invert I and Q samples, the simple signal is working.
    Note2: the signal has been generated with the following C code:

        omega = 2 * M_PI * freq / sample_rate;

    phi = 0;
    for(i = 0; i < n_samples; i++) {
        a.re = cos(phi) * amp;
        a.im = sin(phi) * amp;
        fwrite(&a, 1, sizeof(a), f);
        phi += omega;
        if (phi >= M_PI)
            phi -= 2 * M_PI;
    }

     

    Outputting a 4G signal in 20 MHz

    We can play a 20MHz bandwidth 4G signal in loop. We see the power on all the 20MHz bandwidth. If we synchronize the clock with GPS, we can decode the signal with our 4G analyzer.

     

    LVDS calibration

    We tried to do the LVDS calibration by doing the writes below and using our PRBS checker in FPGA but for now, we couldn't make the calibration work (The PRBS checker never sees a valid signal).

    // code to test the LVDS
reset_chip();
main_init();
spi_write(0x070, 1 << 2);
// Start loop of LVDS read check : the PRBS checker never see a good value.

     

    Is this how we should do ? For info, the init seed of the PRBS checker in our FPGA is 0x0a54